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VX1138/VX1136
HIGH QUALITY PROGRESSIVE VIDEO PROCESSOR AND TIMING CONTROLLER
Headquarters Room B7, 1F, No.1, Li_Hsin Rd. I, Science Based Industrial Park, HsinChu City, 300, Taiwan, R.O.C. Tel : 886-3-5630888 Fax: 886-3-5630889
VXIS Technology Corp. http://www.vxis.com
VXIS Technology Corp. reserves the right to change or modify the information contained herein without notice. Contact VXIS or visit the website to ensure the most recent revision of the document.
VX1138/VX1136
Product Specification High Quality Video Processor
Table of Contents
1 OVERVIEW ___________________________________________________________________ 5 1.1 DESCRIPTION ________________________________________________________________ 5 1.2 APPLICATION ________________________________________________________________ 5 1.3 FEATURES __________________________________________________________________ 6 1.4 BLOCK DIAGRAM _____________________________________________________________ 7 1.4.1 Block Diagram of VX1138 __________________________________________________ 7 1.5 PINOUT DIAGRAM _____________________________________________________________ 8 1.5.1 Pinout Diagram of VX1138 _________________________________________________ 8 1.5.2 Pinout Diagram of VX1136 _________________________________________________ 9 1.6 PIN ASSIGNMENT ____________________________________________________________ 10 1.6.1 Pin Assignment of VX1138 ________________________________________________ 10 1.6.2 Pin Assignment of VX1136 ________________________________________________ 11 1.7 PIN DESCRIPTION ____________________________________________________________ 12 1.8 PACKAGE __________________________________________________________________ 13 2 VIDEO I/O PIN ASSIGNMENT ____________________________________________________ 14 2.1 DIGITAL VIDEO INPUT ASSIGNMENT _____________________________________________ 14 2.2 DIGITAL VIDEO OUTPUT ASSIGNMENT ___________________________________________ 15 3 CLOCK SYSTEM ______________________________________________________________ 16 3.1 REFERENCE CLOCK SETTING FOR PLL INPUT CLOCK __________________________________ 16 4 HOST INTERFACE ____________________________________________________________ 17 5 HARDWARE AND SOFTWARE RESET ____________________________________________ 18 6 VIDEO INPUT SELECTION ______________________________________________________ 19 7 RELACS _____________________________________________________________________ 21 8 FRAME-RATE CONVERSION ____________________________________________________ 22 9 DEINTERLACE _______________________________________________________________ 23 10 COLOR ENHANCEMENT ______________________________________________________ 24 10.1 CONTRAST, BRIGHTNESS, COLOR, AND HUE ADJUSTMENT______________________________ 24 10.2 BLACK-LEVEL EXTENSION (BLE) ________________________________________________ 24 10.3 VIDEO NOISE REDUCTION (VNR)________________________________________________ 24 10.4 SHARPNESS _______________________________________________________________ 24
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P2/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
10.5 COLOR-TRANSIENT IMPROVEMENT (CTI) __________________________________________ 26 10.6 COLOR LOOK-UP TABLE (CLUT) AND GAMMA CORRECTION ____________________________ 26 10.6.1 CLUT ________________________________________________________________ 26 11 VIDEO OUTPUT SECTION _____________________________________________________ 28 11.1 PROGRESSIVE VIDEO OUTPUT SETTING ___________________________________________ 28 11.2 DITHERING ________________________________________________________________ 28 11.3 CLAMPING ________________________________________________________________ 29 11.4 VIDEO OUTPUT TIMING _______________________________________________________ 29 11.5 VIDEO OUTPUT SYNCHRONIZATIONS _____________________________________________ 29 11.6 VIDEO OUTPUT DISPLAY ______________________________________________________ 31 12 ON-SCREEN-DISPLAY (OSD) ___________________________________________________ 32 12.1 OSD INTRODUCTIONS ________________________________________________________ 32 12.2 OSD DISPLAY BLOCKS _______________________________________________________ 32 12.3 OSD OPERATIONS __________________________________________________________ 33 12.4 OSD ATTRIBUTE SETTING _____________________________________________________ 35 12.5 OSD MASKING AND ALPHA-BLENDING ____________________________________________ 37 12.6 OSD MEMORY ACCESS ______________________________________________________ 37 12.6.1 Direct Memory Access ___________________________________________________ 37 12.6.2 Continuous Write Memory Access __________________________________________ 37 13 MEMORY INTERFACE ________________________________________________________ 40 14 TIMING CONTROLLER ________________________________________________________ 41 15 REGISTER DESCRIPTION _____________________________________________________ 42 15.1 PROGRESSIVE VIDEO PROCESSOR REGISTER (CHIP ADDRESS = 0X32) _____________ 42 15.1.1 REGISTER MAP _______________________________________________________ 42 15.1.2.1 Global Registers ______________________________________________________ 46 15.1.2.2 Input Format Registers _________________________________________________ 47 15.1.2.3 Deinterlace Registers __________________________________________________ 51 15.1.2.4 Picture Adjustment Registers ____________________________________________ 51 15.1.2.5 Picture Adjustment Registers ____________________________________________ 54 15.1.2.6 OSD Registers _______________________________________________________ 54 15.1.2.7 Output Format Registers _______________________________________________ 58 15.1.2.8 SDRAM Interface Registers _____________________________________________ 63 15.1.2.9 Relacs Registers______________________________________________________ 63 15.1.2.10 TCON Registers _____________________________________________________ 64
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P3/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
15.1.2.11 sdram bypass Registers _______________________________________________ 66 15.1.2.12 CCD IN Read register _________________________________________________ 67 15.1.2.13 Input signal size register (read) _________________________________________ 67 15.1.2.14 Median filter control register ____________________________________________ 68 15.1.2.15 output Pattern generation control register _________________________________ 68 15.1.2.16 Continuous Write Registers ____________________________________________ 69 16 ELECTRICAL CHARACTERISTICS ______________________________________________ 71 16.1 ABSOLUTE MAXIMUM RATINGS __________________________________________________ 71 16.2 RECOMMENDED OPERATING CONDITIONS _________________________________________ 71 16.3 DC CHARACTERISTICS _______________________________________________________ 72 17 PACKAGE __________________________________________________________________ 73
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P4/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
automatic film mode detection, Edge Preserving Pixel Interpolation, mode frame-rate The and conversion, font-based universal synchronization regeneration, and automatic source VX1138 is a progressive video processor IC, consists of video processor, 3-D deinterlacer, picture enhancement engine, the scaling engine specially designed for video apps, T-con for LCD panel timing control. It receives digitized interlaced video stream (BT. 656 or bt. 601) from video decoder or MPEG video decoder. It also can receive RGB 24-bit video input. VX1138 can perform high quality picture enhancement such as video noise reduction, sharpening, black-level extension, and Gamma correction, and converts it into non-interlaced formats for direct display on progressive devices, such as LCD displays, DTV, projectors, or PC monitors. Its output resolution covers 320x240, 640x480, 720x480 800x480, 800x600, 1024x768, 1280x720, 1280x1024, 1600x1200, VXIS's 1920x1080. VX1138 provides theater quality progressive scan video with innovated Motion Adaptive-3D Deinterlace Algorithm, 3-2 pull down with Portable DVD Car TV Small/middle size LCD TV photoframe surveillance Multimedia panel detection. (OSD), on-screen-display
1 OVERVIEW
1.1 DESCRIPTION
programmable timing control makes it become a highly integrated, most cost-efficient LCD video processor.
1.2 APPLICATION
(SDRAM)
Digital CCIR656/601 RGB/YUV
Progressive display
VX1138
Panel control signals
System Controller
Figure 1.1 Interface for VX1138
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P5/P73
V1.22 090709
VX1138/VX1136
Product Specification 1.3 FEATURES
Support Various Digital Video Input Formats 8-bit interlace ITU-R BT.656 8-bit progressive 656 8-Bit ITU-R BT.601 + Horizontal Sync + Vertical Sync 8-bit Bayer format CCD input, up to 1280x1024 24-bit RGB/YUV progressive input 16-bit Y/UV input
High Quality Video Processor
Support Various Digital Video Output Formats 24/18/16-Bit RGB + Horizontal Sync + Vertical Sync 24/18/16-Bit 4:4:4 YUV + Horizontal Sync + Vertical Sync 16-Bit 4:2:2 YUV + Horizontal Sync + Vertical Sync 8-bit YUV progressive BT.656
Frame rate up-conversion to 60 Hz for PAL & SECAM Motion-Adaptive 3D(with SDRAM) or 2D(without SDRAM) Deinterlace Edge-Preserving Pixel Interpolation Automatic Video Source Detection Embedded Scaling Engine, Supporting Output Resolution 320x240, 640x480, 720x480 800x480, 800x600, 1024x768, 1280x720, 1280x1024, 1600x1200, 1920x1080, ..... Programmable Zoom/Shrink Scale with Anamorphic / Panoramic /4:3 / 16:9 Zoom Support Brightness, Contrast, Saturation, and Hue Adjustment Color Transient Improvement, Adaptive Black-Level Extension, Skin Tone Enhancement. Video Noise Reduction Frequency Directive Picture Sharpening 3-Channel 10-Bit Build-In Color gamma Look-Up Table for Video Fine-Tune Host Interface Compatible with Two-Wire IIC, Serial Interface OSD with 128 Build-in and 64 Programmable Font and Attribute Table, 16 Colors at same Time from 16,777,216-Color Template, Blinking, and Blending R/G/B output port swap & rotation control R/G/B input port swap & rotation control 8 pins of programmable panel timing control signals One 20 MHz crystal, or from CCIR input clock or from RGB input clock as internal reference clock 1.8V / 3.3V power supply with 5V tolerant digital I/O
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P6/P73
V1.22 090709
VX1138/VX1136
Product Specification 1.4 BLOCK DIAGRAM
1.4.1 BLOCK DIAGRAM OF VX1138
High Quality Video Processor
RGB input Format Converter Deinterlacer Scaler Video processor
Output Data Formater
Digital Video Output (R,G,B)
Interlaced / Progressive Digital Video (BT.656/601)
OSD
Reference Clock
Sync/ Panel Timing Generator Clock Synthesizer
Timing Control Signals
Memory controller
Serial Host Interface
(SDRAM)
Micro Controller
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P7/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
1.5 PINOUT DIAGRAM
1.5.1 PINOUT DIAGRAM OF VX1138
SD_D[7] SD_D[6] SD_D[5] SD_D[4] SD_D[3] SD_D[2] SD_D[1] SD_D[0] DVDD_P1 VIVS VIHS VICLK DGND_P1 VID[7] VID[6] VID[5] VID[4] VID[3] VID[2] VID[1] VID[0] SDA SCL RESETB RIN[7] RIN[6] RIN[5] RIN[4] RIN[3] RIN[2] RIN[1] RIN[0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
XTAL_IN XTAL_OUT DVDD_P5 DGND_P5 AGND_PLL AVDD_PLL TEST_ENB SD_WE SD_RAS SD_CAS SD_A[10] SD_A[0] SD_A[1] SD_A[2] SD_A[3] SD_A[4] SD_A[5] SD_A[6] SD_A[7] SD_A[8] SD_A[9] DVDD_P4 SD_CLK DGND_P4 POL STVL OEV CKV STVR STHL INCLK_SEL[1] INCLK_SEL[0]
VX1138
SD_BA SD_D[8] SD_D[9] SD_D[10] SD_D[11] SD_D[12] SD_D[13] SD_D[14] SD_D[15] STHR LD BIN[0] BIN[1] BIN[2] BIN[3] BIN[4] BIN[5] BIN[6] BIN[7] ROUT[7] ROUT[6] ROUT[5] ROUT[4] ROUT[3] ROUT[2] ROUT[1] ROUT[0] DVDD_P3 VOVLK DGND_P3 VOHS VOVS
Confidential
LDOVDD LDO18 LDOVSS GIN[7] GIN[6] GIN[5] GIN[4] GIN[3] GIN[2] GIN[1] GIN[0] DVDD_P2 RGBIN_VS RGBIN_HS RGBIN_CLK DGND_P2 BOUT[0] BOUT[1] BOUT[2] BOUT[3] BOUT[4] BOUT[5] BOUT[6] BOUT[7] GOUT[0] GOUT[1] GOUT[2] GOUT[3] GOUT[4] GOUT[5] GOUT[6] GOUT[7]
P8/P73 V1.22 090709
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VX1138/VX1136
Product Specification
1.5.2 PINOUT DIAGRAM OF VX1136
High Quality Video Processor
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
XTAL_IN XTAL_OUT DVDD_P5 DGND_P5 AGND_PLL AVDD_PLL TEST_ENB DVDD_P4 DGND_P4 POL STVL OEV CKV STVR STHL INCLK_SEL[1] INCLK_SEL[0] DVDDC
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LDO18 LDOVSS DVDD_P2 DGND_P2 BOUT[0] BOUT[1] BOUT[2] BOUT[3] BOUT[4] BOUT[5] BOUT[6] BOUT[7] GOUT[0] GOUT[1] GOUT[2] GOUT[3] GOUT[4] GOUT[5] GOUT[6] GOUT[7]
P9/P73
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DVDD_P1 VIVS VIHS VICLK DGND_P1 VID[7] VID[6] VID[5] VID[4] VID[3] VID[2] VID[1] VID[0] SDA SCL RESETB LDOVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VX1136
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
STHR LD ROUT[7] ROUT[6] ROUT[5] ROUT[4] ROUT[3] ROUT[2] ROUT[1] ROUT[0] DVDD_P3 VOVLK DGND_P3 VOHS VOVS -
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
1.6 PIN ASSIGNMENT
1.6.1 PIN ASSIGNMENT OF VX1138 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name SD_D[7] SD_D[6] SD_D[5] SD_D[4] SD_D[3] SD_D[2] SD_D[1] SD_D[0] DVDD_P VIVS VIHS VICLK DGND_P VID[7] VID[6] VID[5] VID[4] VID[3] VID[2] VID[1] VID[0] SDA SCL RESETB RIN[7] RIN[6] RIN[5] RIN[4] RIN[3] RIN[2] RIN[1] RIN[0] Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name LDO_VDD LDO_V18 LDO_VSS GIN[7] GIN[6] GIN[5] GIN[4] GIN[3] GIN[2] GIN[1] GIN[0] DVDD_P RGBIN_VS RGBIN_HS RGBIN_CLK DGND_P BOUT[0] BOUT[1] BOUT[2] BOUT[3] BOUT[4] BOUT[5] BOUT[6] BOUT[7] GOUT[0] GOUT[1] GOUT[2] GOUT[3] GOUT[4] GOUT[5] GOUT[6] GOUT[7] Pin # 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name_ VOVS VOHS DGND_P VOCLK DVDD_P ROUT[0] ROUT[1] ROUT[2] ROUT[3] ROUT[4] ROUT[5] ROUT[6] ROUT[7] BIN[0] BIN[1] BIN[2] BIN[3] BIN[4] BIN[5] BIN[6] BIN[7] LD STHR SD_D[15] SD_D[14] SD_D[13] SD_D[12] SD_D[11] SD_D[10] SD_D[9] SD_D[8] SD_BA Pin # 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name INCLK_SEL[0] INCLK_SEL[1] STHL STVR CKV OEV STVL POL DGND_P SD_CLK DVDD_P SD_A[9] SD_A[8] SD_A[7] SD_A[6] SD_A[5] SD_A[4] SD_A[3] SD_A[2] SD_A[1] SD_A[0] SD_A[10] SD_CAS SD_RAS SD_WE TEST_ENB AVDD_C AGND_C DGND_P DVDD_P XTAL_OUT XTAL_IN
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P10/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
1.6.2 PIN ASSIGNMENT OF VX1136 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name DVDD_P VIVS VIHS VICLK DGND_P VID[7] VID[6] VID[5] VID[4] VID[3] VID[2] VID[1] VID[0] SDA SCL RESETB LDOVDD Pin # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name LDO18 LDOVSS DVDD_P DGND_P BOUT[0] BOUT [1] BOUT [2] BOUT [3] BOUT [4] BOUT [5] BOUT [6] BOUT [7] GOUT [0] GOUT [1] GOUT [2] GOUT [3] GOUT [4] GOUT [5] GOUT [6] GOUT [7] Pin # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name_ VOVS VOHS DGND_P VOCLK DVDD_P ROUT[0] ROUT[1] ROUT[2] ROUT[3] ROUT[4] ROUT[5] ROUT[6] ROUT[7] LD STHR Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name DVDD_C INCLK_SEL[0] INCLK_SEL[1] POLSTHL STVR CKV OEV STVL POL DGND_P DVDD_P TEST_ENB AGND_C AGND_C DGND_P DVDD_P XTAL_OUT XTAL_IN
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P11/P73
V1.22 090709
VX1138/VX1136
Product Specification 1.7 PIN DESCRIPTION
Video Input Pins Name VID [7:0] VIHS VIVS VICLK RIN[7:0] GIN[7:0] BIN[7:0] RGBIN_VS RGBIN_HS RGBIN_CLK Type I I I I I I I I I I Description Digital Video Input Data(BT 656/601) Digital Video Input Horizontal Synchronization Digital Video Input Vertical Synchronization Digital Video Input Clock Red input data Green input data Blue input data RGB input vertical synchronization RGB input horizontal synchronization RGB input clock Notes
High Quality Video Processor
Video Output Pins Name ROUT [7:0] GOUT [7:0] BOUT [7:0] VOHS / GPO1 VOVS / GPO0 VOCLK STHR STHL / GPO1 STVR STVL / GPO0 POL LD CKV OEV / GPO2 Type OTS1 OTS1 OTS1 O1 O1 O2 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 Description R/V/Pr Digital Video Output G/Y/BT656 Digital Video Output B/U/Pb Digital Video Output Video Output Horizontal Synchronization / GPO1 Video Output Vertical Synchronization / GPO0 Video Output Clock / BT656 Output Clock Horizontal start pulse output Horizontal start pulse output GPO1 Vertical start pulse output Vertical start pulse output GPO0 Polarity inversion control Latch control for source driver Shift clock for gate driver Output Enable signal for gate driver GPO2 Notes
External SDRAM I/O Pins Name SDRAM_D [15:0] SDRAM_A [10:0] SDRAM_CLK SDRAM _RAS SDRAM _CAS SDRAM _WE SDRAM_BA Type I/O1 OT1 OT2 OT1 OT1 OT1 OT1 Description SDRAM Data Bus SDRAM Address Bus SDRAM Clock SDRAM Row Address Strobe (Active Low) SDRAM Column Address Strobe (Active Low) SDRAM Write Enable (Active Low) SDRAM Bank Notes
Miscellaneous I/O Pins Name Type Description Notes
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P12/P73
V1.22 090709
VX1138/VX1136
Product Specification
/RESETB XTAL_OUT XTAL_IN SDA SCL /TEST_ENB INCLK_SEL[1:0] IS XO XI I/O1 IS IPU I Chip Reset (Active Low) Crystal Output Crystal Input Host Interface Serial Data / Address Host Interface Serial Clock Test Mode Enable (Active Low) reference clock select for internal PLL
High Quality Video Processor
Power Pins Name AVDD_C AGND_C DVDD_P DGND_C LDOVDD LDOVSS LDO18 Type Description P18 G P33 G P33 G P18 Analog 1.8V Supply For PLL CORE Analog Ground For PLL CORE Digital 3.3V Supply For I/O Digital Ground For CORE 3.3V power for LDO LDO ground 1.8V output from LDO Notes Qty: 2 Qty: 2 Qty: 6 Qty: 7 Qty: 1 Qty: 1 Qty: 1
1.8 PACKAGE
1138 1136 128-Pin LQFP 80-Pin LQFP
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P13/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
2 VIDEO I/O PIN ASSIGNMENT
2.1 DIGITAL VIDEO INPUT ASSIGNMENT
The VX1138 digital video interface is compatible with extensive digital video input and output standard formats mostly used by current video transmission methods. As for input, VX1138 directly supports interlaced 8-bit YUV with (ITU-R BT.656) or without (ITU-R BT.601) embedded synchronization, It also supports progressive 8-bit YUV input and 16-bit Y/UV, 24-bit YUV, 24-bit RGB input. The pin arrangement for each format is defined in Table 2.1.
Table 2.1 Digital Video Input Pin Assignment Pin Name VID [7] VID [6] VID [5] VID [4] VID [3] VID [2] VID [1] VID [0] RIN [7] RIN [6] RIN [5] RIN [4] RIN [3] RIN [2] RIN [1] RIN [0] GIN [7] GIN [6] GIN [5] GIN [4] GIN [3] GIN [2] GIN [1] GIN [0] BIN [7] BIN [6] BIN [5] BIN [4] BIN [3] BIN [2] BIN [1] BIN [0] I/O Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Digital Input 16-bit 24-bit YUV YUV Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] UV[7] V[7] UV[6] V[6] UV[5] V[5] UV[4] V[4] UV[3] Y[3] UV[2] V[2] UV[1] V[1] UV[0] V[0] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] U[7] U[6] U[5] U[4] U[3] U[2] U[1] U[0] 24-bit RGB
8-bit YUV YUV [7] YUV [6] YUV [5] YUV [4] YUV [3] YUV [2] YUV [1] YUV [0] -
R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
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P14/P73
V1.22 090709
VX1138/VX1136
Product Specification 2.2 DIGITAL VIDEO OUTPUT ASSIGNMENT High Quality Video Processor
As for output, VX1138 sends progressive video data out with 24/18/16-bit 4:4:4 RGB/YUV digital formats or 16-bit 4:2:2 YUV format or 8-bit YUV format through pins DR_V, DG_Y, and DB_U. The pin assignment for each format is defined in Table 2.2
Table 2.2 Digital Video Output Pin Assignment I/O Type O O O O O O O O O O O O O O O O O O O O O O O O 16-bit 4:2:2 YUV UV [7] UV [6] UV [5] UV [4] UV [3] UV [2] UV [1] UV [0] Y [7] Y [6] Y [5] Y [4] Y [3] Y [2] Y [1] Y [0] Digital Output 16-bit RGB565 / YUV R/Pr/V [4] R/Pr/V [3] R/Pr/V [2] R/Pr/V [1] R/Pr/V [0] G/Y [5] G/Y [4] G/Y [3] G/Y [2] G/Y [1] G/Y [0] B/Pb/U [4] B/Pb/U [3] B/Pb/U [2] B/Pb/U [1] B/Pb/U [0] 18-bit RGB666 / YUV R/Pr/V [5] R/Pr/V [4] R/Pr/V [3] R/Pr/V [2] R/Pr/V [1] R/Pr/V [0] G/Y [5] G/Y [4] G/Y [3] G/Y [2] G/Y [1] G/Y [0] B/Pb/U [5] B/Pb/U [4] B/Pb/U [3] B/Pb/U [2] B/Pb/U [1] B/Pb/U [0] 24-bit RGB / YUV R/Pr/V [7] R/Pr/V [6] R/Pr/V [5] R/Pr/V [4] R/Pr/V [3] R/Pr/V [2] R/Pr/V [1] R/Pr/V [0] G/Y [7] G/Y [6] G/Y [5] G/Y [4] G/Y [3] G/Y [2] G/Y [1] G/Y [0] B/Pb/U [7] B/Pb/U [6] B/Pb/U [5] B/Pb/U [4] B/Pb/U [3] B/Pb/U [2] B/Pb/U [1] B/Pb/U [0]
Pin Name ROUT [7] ROUT [6] ROUT [5] ROUT [4] ROUT [3] ROUT [2] ROUT [1] ROUT [0] GOUT [7] GOUT [6] GOUT [5] GOUT [4] GOUT [3] GOUT [2] GOUT [1] GOUT [0] BOUT [7] BOUT [6] BOUT [5] BOUT [4] BOUT [3] BOUT [2] BOUT [1] BOUT [0]
8-bit YUV YUV[7] YUV[6] YUV[5] YUV[4] YUV[3] YUV[2] YUV[1] YUV[0] -
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P15/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
3 CLOCK SYSTEM
3.1 REFERENCE CLOCK SETTING FOR PLL INPUT CLOCK
All the clocks required for vx1138 can be generated from internal PLL. The reference input clock for PLL comes from video input clock(VICLK or RGBIN_CLK) or external Crystal, depends on user's requirement. This can be set by pin ICLK_SEL[1:0]. When the value is set to 2'b00, the default value, the system auto detect the existed clock, according to the order VICLK, RGBINCLK, XTAL_IN. when the value is set to 2'b01, the reference clock comes from pin VICLK. When the value is set to 2'b10, the reference clock comes from RGBIN_CLK. When the value is set to 2'b11, it comes from external crystal pin XTAL_IN. Table 3.1 list the reference clock setting for PLL.
Table 3.1 PLL input Reference Clock Configuration INCLK_SEL Ref_clock 00 Auto_detect 01 VICLK 10 RGBINCLK 11 XTALIN
AUTO_DETECT is detected by the order VICLK, RGBINCLK, XTALIN REF_CLOCK is used for internal PLL reference input clock and iic clock
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P16/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
4 HOST INTERFACE
The VX1138 host interface uses two-wire IIC compatible interface protocol, one for clock, and one for multiplexed data/address. Input pin SCL is used for host clock input while input/output pin SDA is for multiplexed host data and address signal. VX1138 requires 2 chip address to control the video decoder and progressive video processor parts. When write to the progressive video processor part(deinterlace,scaler,..), the Chip Write Address is 0x32, and Chip Read Address is 0x33.
Once chip write and read addresses are configured, the host command byte sequence can be transfer to VX1138 via the serial interface. The byte sequence consists of a CHIP ADDRESS, a REGISTER ADDRESS, followed by a number of DATA BYTES. The CHIP ADDRESS and REGISTER ADDRESS must be always provided by the host, usually a micro-controller, and the DATA BYTES are provides by host for host-writings and by VX1138 for host-readings.
Chip Address Command Start
Register Address A
Data Byte for A
Data Byte for A+1 Command Stop
Figure 4.1 Host Command Byte Sequence
As shown above, the first DATA BYTE following REGISTER ADDRESS A is assigned or read to/from register address A, the DATA BYTE behind will be assigned/read to/from register address A+1, and so on. So for large host-writings such as chip initialization, only the initial register address needs to be specified once to complete whole host writing operations. In this manner user can save a lot of host command cycles in complicated applications.
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P17/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
5 HARDWARE AND SOFTWARE RESET
VX1138 can be reset to initial stage in two ways. One is through the hardware pin, RESETB; by asserting RESETB pin to ground voltage, entire chip will be reset to its initial states. The other way is through the host interface by writing to register RST1 (01h). Writing value 5Ah to RST1, called software reset, will generate an internal reset pulse signal similar to RESETB to initialize the entire chip.
Similar to writing 5Ah to RST1, writing A5h to RST1 will reset entire chip except control registers programmed by host interface. The use of A5h writing often occurs after initial register programming or mid-state register changes to assure the chip working from the initial state.
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6 VIDEO INPUT SELECTION
The VX1138 accepts 6 types of digital video formats as input data stream, it can be set by changing the value of register bits INFMT [2:0]. Following Table 6.1 shows VX1138's acceptable digital video input formats. For their pin assignment, please review CHAPTER 2 DIGITAL VIDEO I/O PIN ASSIGNMENT.
Table 6.1 Digital Video Input Format Selection INFMT [2:0] 000 001 010 011 110 111 Digital Video Input Format 8-Bit ITU-R BT.656 8-Bit ITU-R BT.601 Digital Video Data With external H_sync and V_sync input 16-bit Y/UV 4:2:2 data with external sync pin 16/18/24-bit Y/U/V 4:4:4 progressive data 8-bit CCD Bayer format input (up to 1280 pel/line) 24-bit RGB progressive input
If the input data of above format is progressive, set the register bit PG_IN to 1.
The VX1138 supports all NTSC, PAL, SECAM, and square pixel video standard. For each standard the number of lines per field and pixels per line vary according to their specifications. These standards are summarized as follows.
Table 6.2 Video input standard Input format Horizontal Total Pixels Per Line Vertical Total Lines Per Frame Frame Rate NTSC PAL/SECAM 858 864 525 625 60 50
It can automatically detect the digital video format by setting the AUTO_NP on. The digital video source also can be forced to NTSC,PAL,SECAM by disabling AUTO_NP, and then manually set register bit SET_NP to 1 for PAL/SECAM, or 0 for NTSC. To enter the square pixel mode, user needs to enable the register bit SQ_EN. The NTSC/PAL/SECAM auto-detection function also works under square pixel mode.
For ITU-R BT.656 format, the UV byte could be unsigned signal, which is in the range from 0 to 255, or signed 2's compliment signal, which is in the range from -128 to 127. Set the register bit UVFMT to define above two types of UV data for VX1138.
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If the digital video input format (INFMT) is 001, 011, the additional synchronization signals VIHS and VIVS must be used along with the digital video input data. The VIVS pin depending on the register INSYN could be configured as one of four types of vertical synchronization signals, equaled VSYNC, non-equaled VSYNC, equaled FIELD, and non-equaled FIELD. The "Equaled" signal means the vertical synchronization duration is in the same length for EVEN and ODD field. The "Non-Equaled" signal means the vertical synchronization duration is longer for ODD field than EVEN field.
VIHS_OFST
L
L = 138 Pixels for NTSC L = 144 Pixels for PAL
VIHS
Line Data Bytes Begin Data During VIHS L
Digital Video Input Data
Valid Data 720 Pixels
Figure 6.1 Digital Video Input Signals
Shown in above figure, the VX1138 takes 720 pixels in each horizontal line as the active data. In NTSC system, the number of total pixels in each line is 858. This results in that the length of the horizontal synchronization period is 138 pixels and during this period of time, the bytes in the data channel will be ignored, therefore. Register VIHS_OFST is used to fine-tune the screen position of valid data period. Its range is from -127 to 127 and default value is 0.
For some specific applications, the number of pixels in each horizontal line is not the same as NTSC or PAL/SECAM systems, such as sub-carrier frequency domain video data. To compensate this difference, the VX1138 has an option to manually set the horizontal length. To enable this feature, the register MIL_EN must be enabled first, then user can specify target number of length in pixel to register MHIL. Note that since the internal line buffer length is still limited to 720 pixels, Manually setting larger number of length will truncate more pixels in each line.
Usually the input data is latched per cycle of the video input clock. For some cases that the data should be latched every two cycles of the video input clock, such as latching 16-bit YC by 27 MHz clock, program the register VICLKF to zero.
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7 RELACS
Relacs is VXIS's intellectual invention of high-quality and low-cost scaler. It utilizes separate algorithms for up-scaling and down-scaling processes and sharing the usage of line buffers. For output resolution setting, refer to the following table for some default setting of register SMODE.
Table 7.1 Output Resolution Setting
SMODE 0 1 2 3 4 5 6 7 8 9 10~15 No Scaling Down-Scaling to VGA (640 x 480) Up-Scaling to SVGA (800 x 600) Up-Scaling to XGA (1024 x 768) Up-Scaling to SXGA (1280 x 1024) Up-Scaling to 720P (1280 x 720) Up-Scaling to WSVGA (1366 x 768 ) Up-Scaling to WVGA (1600x1200) Up-Scaling to 1080P (1920x1080) Up-Scaling to WVGA (800 x 480) Manual model Output Resolution
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8 FRAME-RATE CONVERSION
Programming frame-rate conversion in VX1138 is simple and intuitive. Since the frame-rate conversion is done in the deinterlace stage in VX1138, the frequency of deinterlace clock is the parameter to fine-tune the video output frame-rate with respect to the input videos.
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9 DEINTERLACE
The VX1138's deinterlace engine computes the insertion data from three-dimension information, containing three spatial and one temporal dimensions. Without external SDRAMs (MEM_USAGE = 00b; DEINT_MDOE = 10b, only for digital video input mode), the deinterlacer can performs Edge-Preserving Pixel Interpolation capable of detecting from 90-degree to 14-degree edge for most cost-effective application. With the aid of optional external SDRAMs as frame memory (MEM_USAGE = 01b; DEINT_MDOE = 00b), the VX1138 performs not only above Edge-Preserving Pixel Interpolation but also VXIS's most advanced Motion-Adaptive 3-D De-Interlace, which will lead theater quality video scheme in the conventional HDTV or monitor set.
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10 COLOR ENHANCEMENT
10.1 CONTRAST, BRIGHTNESS, COLOR, AND HUE ADJUSTMENT
The VX1138 supports essential color adjustment through the registers, CONTRAST, BRIGHTNESS, COLOR, and HUE. Among those, the CONTRAST and the BRIGHTNESS can also be adjusted independently in R / G / B manner by the registers, R_CONTRAST, G_CONTRAST, B_CONTRAST, R_BRIGHTNESS, G_BRIGHTNESS, and B_BRIGHTNESS.
10.2 BLACK-LEVEL EXTENSION (BLE)
Basic idea of black level extension is to enhance the contrast of the luminance in the dark potion of the picture. As the result, the average luminance in the dark potion will be extended to darker level non-linearly while the luminance in bright potion remains unchanged. The advantage of this function is to make the object more solid, apparent, and noticeable to the viewers. The BLE function works adaptively, depending on the average luminance of the picture.
10.3 VIDEO NOISE REDUCTION (VNR)
The VX1138 contains video noise reduction (VNR) engine specifically removing Gaussian noise and mid-band interception noise, which commonly occurs in video transmission channels. Figure 10.3.1 shows the block diagram of VX1138's VNR engine. VNR function is enabled from the register VNR.
10.4 SHARPNESS
The VX1138 offers three peaking filters for different frequency response in horizontal sharpness engine. The gain for each filter is adjustable from 0 to 14 dB and individually controlled with registers, PEAK_ADJ1, PEAK_ADJ2, and PEAK_ADJ3 (Figure 10.4.1). For peaking filter 1, 2, and 3, each respectively amplifies 1/2, 1/4, and 1/6 of sampling frequency (27 MHz). Following the three peaking filters is a clipping filter to suppress video gain after peaking filters and reduce noise. The clipping filter is adjustable with the registers PEAK_CLIP_MIN and PEAK_CLIP_MAX. If the input value (summed
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gain) of the clipping filter is smaller than PEAK_CLIP_MIN, the output value of the clipping filter is clipped to zero. If the input value is between PEAK_CLIP_MIN and PEAK_CLIP_MAX, the output value of the clipping filter is linearly (input value - PEAK_CLIP_MIN). If the input value is larger than PEAK_CLIP_MAX, the output value of the clipping filter is clipped to (PEAK_CLIP_MIN PEAK_CLIP_MAX).
Figure 10.4.1 Frequency Response for Peaking Filters
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Product Specification 10.5 COLOR-TRANSIENT IMPROVEMENT (CTI)
For most video solutions, video content in chrominance domain are often with less care due to human eye's neglect of color variations. Therefore, we sometimes found that the picture is implicitly dirty and foggy especially when we observing the video patterns or color-bars. The color-transient improvement (CTI) engine in VX1138 is made to recover this imperfectness of video presentation and perform sharp and keen edges for every objects and overall clearer video to the viewers.
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10.6 COLOR LOOK-UP TABLE (CLUT) AND GAMMA CORRECTION
The VX1138 provides method to finely manipulate video sequence, color look-up table (CLUT). CLUT is made of three embedded SRAMs and requires initial SRAM programming with continuous-write scheme of host interface. Register CLUT_MODE enable the usage of CLUT.
10.6.1 CLUT
Widely used in many applications, the VX1138 equips a build-in 3-channel 10-bit color look-up table (CLUT). The CLUT contains three 256 x 10-bit SRAMs, one for each of R/Pr, G/Y, and B/Pb channels. For each channel, the SRAM acts as an one-to-one mapping array and reads 8-bit data as index, and maps into 10-bit data as SRAM data output. By manipulating every single cell of SRAMs, user can make neat changes of the color mapping for each single level of 256 color levels in each channels. Using the CLUT, all the picture/video related adjustments such as color adjustment, gamma, and color temperature can be accomplished with specifically programmed mapping data. CLUT_MODE and the datawidth register CLUT_WIDTH, must be set before using the CLUT. Programming the CLUT is intuitive through the continuous-write registers. First, program the destination SRAM to one or all of the R/Pr, G/Y, B/Pb channels with the register CW_DEST. Next, write the initial 8-bit address to register CW_INIT_ADDR. Then, in sequence write the data into the register CW_DATA, and the internal host interface controller will automatically write this data into the designated SRAM after a short period of time, and increment the address by 1 after each internal SRAM writing. If the CLUT data width is set to 10-bit, then the internal automatic SRAM writing operation will take place at every two host writing of CW_DATA (Figure 10.6.1.2).
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CLUT Sequence for 8-Bit Data Loading Host Command Sequence Internal SRAM Writing Action CLUT Sequence for 10-Bit Data Loading Host Command Sequence Internal SRAM Writing Action
CW_DEST CW_INIT _ADDR CW_DATA 0 High Byte CW_DATA 0 Low Byte CW_DATA 1 High Byte CW_DATA 1 Low Byte CW_DATA 2 High Byte CW_DEST CW_INIT _ADDR CW_DATA 0 CW_DATA 1 CW_DATA 2 CW_DATA 3 CW_DATA 4
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SRAM Data 0 Writing
SRAM Data 1 Writing
SRAM Data 2 Writing
SRAM Data 3 Writing
SRAM Data 0 Writing
SRAM Data 1 Writing
Figure 8.6.1.2 CLUT Programming Sequence Through Host Interface
Note that the CLUT always maps the video in the color domain of analog output port. This means when the analog output port is set to RGB, CLUT mapping is in RGB domain, and when the analog output is set to YPbPr or YUV, CLUT mapping is in YPbPr or YUV domain. Also, as shown in Figure 10.6.1.3 that the value stored in the SRAM can be in 10-bit range (CLUT_WIDTH = 1), or in 8-bit range (CLUT_WIDTH = 0) in RGB or YUV domain mappings. But note that due to synchronization insertion to Y channel, in YPbPr domain CLUT only supports 8-bit mappings.
1023
255 767
255
0 8-Bit Data 511
0 8-Bit Data
Y Domain Mapping
255
255
255
255
0 8-Bit Data
0 10-Bit Data or 8-Bit Data
0 8-Bit Data
0 8-Bit Data
RGB or YUV Domain Mapping
PbPr Domain Mapping
Figure 10.6.1.3 CLUT Mappin
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11 VIDEO OUTPUT SECTION
11.1 PROGRESSIVE VIDEO OUTPUT SETTING
The VX1138 generates variety of digital video outputs formats. It supports digital output in 24/18/16-bit RGB, 4:4:4 YPbPr (with embedded horizontal and vertical synchronization on Y), 4:4:4 YUV (with additional HSYNC and VSYNC pins), or 16-bit 4:2:2 YUV formats. For digital video I/O pin assignment, please see "Chapter 2 DIGITAL VIDEO I/O PIN ASSIGNMENT". Format selection of progressive digital output ports is done through setting of register OFMT. For 8-bit CCIR656 data output, the output format is set to YUV 4:4:4 format (OFMT=3).
Table 11.1.1 Progressive Video Output Format OFMT Output Format 0 Digital Port 1 2 3 3-Channel RGB (df.) 3-Channel 4:4:4 YPbPr (with embedded horizontal and vertical synchronization on Y 2-Channel 4:2:2 YUV (with additional HSYNC and VSYNC pins) 3-Channel 4:4:4 YUV (with additional HSYNC and VSYNC pins)
11.2 DITHERING
When the output format is determined, there is a dithering option provided in 4:4:4 RGB / YPbPr / YUV digital video output formats. For users who are limited to accept 24/18/16-bit digital videos, two approaches can be selected, either simply truncate the 24-bit output data by connecting partial bits of digital video output, or dither the 24-bit output data by setting register DITHER (Table 11.2.1). The dithering algorithm used in the VX1138 is by applying error diffusion calculation to the data and will effectively reduce the boundary effect in low-resolution displays.
Table 11.2.1 Dithering Options DITHER 0 1 2 3 Dithering Option (G/Y : B/Pb/U : R/Pr/V) Disable Dithering to 18-bits (6-bits : 6-bits : 6-bits) Dithering to 24-bits (8-bits : 8-bits : 8-bits) Dithering to 16-bits (6-bits : 5-bits : 5-bits)
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11.3 CLAMPING
The VX1138 has an option to set the digital video output level in ITU-R BT.601 range, ITU-R BT.656 range, or simply in 0-255 8-bit full range. For ITU-R BT.601 standard, luminance channel (Y) is in the range of 16-235, and chrominance channel (UV) is in the range of 16-240. For ITU-R BT.656 standard, luminance (Y) and chrominance channel (UV) are in the range of 1-254. See the register CLAMP for details.
11.4 VIDEO OUTPUT TIMING
For digital video output, all the digital video output datas are valid at the falling edge of the video output clock VOCLK.
Figure 11.4.1 Video Output Timing
11.5 VIDEO OUTPUT SYNCHRONIZATIONS
All the video output synchronization signals, HSYNC, VSYNC, or GCSYNC, of VX1138 are adjustable with respect to output format, frequency, and resolutions. Basically the horizontal synchronization (HSYNC) asserts on every horizontal line's boundary; vertical synchronization (VSYNC) asserts on every frame's boundary; and general composite synchronization (GCSYNC) acts as the combination of horizontal and vertical synchronizations (Figure 11.5.1).
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HSYNC
VSYNC
GCSYNC
Figure 11.5.1 Video Output Synchronizations
The adjustment of synchronization-width of HSYNC and VSYNC is through the registers HS_WIDTH and VS_WIDTH. The actual length of synchronization-width of HSYNC is HS_WIDTH in pixels, and VSYNC is (1 + VS_WIDTH) in lines.
HSYNC and VSYNC are always available at pins. GCSYNC is shared with HSYNC and switched by the register VOHS_SEL
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11.6 VIDEO OUTPUT DISPLAY
Two essential elements, screen shifting and masking, control the VX1138 video output display. The screen shifting function is activated by changing the horizontal shifting register HSHIFT, and vertical shifting register VSHIFT. Setting larger value of HSHIFT moves the picture rightward; and setting larger value of VSHIFT moves the picture downward. Also, the screen masking function is activated by setting the registers BOTTOM_MASK, TOP_MASK, LEFT_MASK, and RIGHT_MASK. The VX1138's output display region with its synchronization and control parameters (screen shifting and screen masking) is summerized in Figure 11.6.1.
Horizontal Total Length HSYNC
HBLANK Horizontal Active Length LEFT_MASK RIGHT_MASK VBLANK VSYNC Vertical Active Length
Progressive Display Screen TOP_MASK Vertical Total Length
Active Region
BOTTOM_MASK
Figure 11.6.1 Output Display Region
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12 ON-SCREEN-DISPLAY (OSD)
12.1 OSD INTRODUCTIONS
The VX1138 integrates VXIS's font-attribute-based on-screen display (OSD) unit, which can display a total of up to 256 characters in a single screen, with each font in 16 pixels x 20 pixels format. The embedded font Random-Access-Memory (RAM) and Read-Only-Memory (ROM) let user select characters from up to 192 fonts, 128 build-in and 64 programmable fonts. The attribute bits programming let user designate arbitrary spectacular menu, closed caption, even games from 16,777,216 colors, blinking, Italic font, underline font, and many artistic features.
12.2 OSD DISPLAY BLOCKS
The build-in OSD system divides the screen display into three basic sections, the title, content, and bottom blocks, and the user can customize the size and position for each display block by host commands (Figure 12.2.1).
(OSDT_POSX, OSDT_POSY) Title Block
(OSDC_POSX, OSDC_POSY)
Content Block
(OSDB_POSX, OSDB_POSY) Bottom Block TV/Monitor Screen
Figure 12.2.1 OSD Display Blocks
The title and bottom blocks are restricted to display one line of text commonly for header or page notes;
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and the content block displays multiple lines of text for main OSD information. The sizes and the positions for each individual block are adjustable through registers (Table 12.2.1). Each displaying block cannot be overlapped with others. For details of the register setting, check OSD section in register description chapter.
Table 12.2.1 Position and Size Registers Register OSDT_POSX OSDC_POSX OSDB_POSX OSDT_SIZEX OSDC_SIZEX OSDB_SIZEX OSDT_POSY OSDC_POSY OSDB_POSY N/A OSDC_SIZEY N/A Description Position registers for title block Position registers for content block Position registers for bottom block Size registers for title block Size registers for content block Size registers for bottom block
12.3 OSD OPERATIONS
The VX1138's OSD unit is font-based entry. All information that is going to be shown in the screen must be translated into fonts, which is in 16 pixel x 20 pixel resolution each, then put into the screen.
There are two types of OSD memories embedded in VX1138. One is called the "font memory", which stores all the fonts currently being used on the screen. The font memory consists of one 128-font ROM (2560 x 16-bit) for commonly used fixed fonts, and one 64-fonts RAM (1280 x 16-bit) for user-programmable fonts (Table 12.3.1). If utilizing maximum amount of the memory, there are up to 192 fonts can be repeatly shown in the single page.
Table 12.3.1 Font Memory Table Index (Hex) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Character Index (Hex) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Character Index (Hex) 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh Character Index (Hex) 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Character
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Index (Hex) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh Character Index (Hex) 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh Character Index (Hex) 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh Character Index (Hex) 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh Character Index (Hex) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh Character User-Programmable Fonts
Index (Hex) 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Character User-Programmable Fonts
Index (Hex) A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh Character User-Programmable Fonts
Index (Hex) B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh Character User-Programmable Fonts
Index (Hex) C0h C1h C2h C3h C4h C5h C6h C7h C8h Character CR 2B 3B 4B 5B 6B 7B 8B 9B
CR: Character Return / Line Feed nB: Number of Space Characters
Another type of memory is called the "command memory", which stores the sequence and the attribute of the font that is appearing on the screen. The command memory consists of two 256 x 8-bit RAMs in two modes (Table 12.3.2). In COLR mode, the command memory stores 256 font indexes with 8-bit attributes of blinking, and sixteen colors for foreground and background; and in CCAP mode, the command memory stores 256 font indexes each with 8-bits attributes of blinking, Italic font option, underline font option, eight colors for foreground, and four colors for background.
Table 12.3.2 Command Memory Configuration Register CCMODE Description Note 0 1 COLR Mode Stores 256 font indexes with attribute for color support CCAP Mode Stores 256 font indexes with attribute for closed caption support
To generate OSD in either mode, the command memory needs to be well programmed. It is divided into title, content, and bottom sections of which initial address pointed by the registers OSDT_MADR,
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OSDC_MADR, and OSDB_MADR (Figure 12.3.1). From the initial address in each section, fill in the indexes of fonts in designated sequence, and the font will appear on the screen consecutively at the next frame. Sections allocated in the command memory can be overlaped with others.
Addr. OSDT_MADR 00h 01h 02h 03h . . OSDC_MADR 15h 16h 17h 18h 19h 1Ah . . OSDB_MADR 70h
Indexes from Font Memory 15h (V) 17h (X) 08h (I) 12h (S) . . 07h(H) 1Eh (e) 25h (l) 25h (l) 28h (o) 43h (!) . . 0Eh (O) 0Ah (K)
Attribute Setting
Attribute for V Attribute for X Attribute for I Attribute for S
VXIS
Attribute for H Attribute for e
Hello!
Attribute for l Attribute for l Attribute for o
OK
Attribute for !
Attribute for O Attribute for K
Figure 12.3.1 OSD Command Memory
12.4 OSD ATTRIBUTE SETTING
Each font displayed on the screen has its own 8-bit attributes for blinkings, colors, and special font formats. They are slightly different in CLOR mode and CCAP mode (Table 12.4.1).
Table 12.4.1 Attribute Bits Table Bit 7 6 5 BG Palette Color Index [2] BG Palette Color Index [1] CLOR Mode Blinking On Italic Font On BG Color Index [1] CCAP Mode
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4 3 2 1 0 BG Palette Color Index [0] FG Palette Color Index [3] FG Palette Color Index [2] FG Palette Color Index [1] FG Palette Color Index [0]
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BG Color Index [0] Underline Font On FG Palette Color Index [2] FG Palette Color Index [1] FG Palette Color Index [0]
There are sixteen blinking-rate options from 0.5 Hz to 7.5 Hz defined in the register, OSD_BLINK. The blinking-rate relates to the OSD_BLINK according to the following equation.
OSD Blinking Rate =
30 Hz OSD_BLINK x 4
The OSD unit has sixteen build-in color palettes each can be fine adjusted from 24-bit color space (16,777,216 colors). Color palette programming can be achieved through the registers, OSD_CP_INDEX, OSD_CP_R, OSD_CP_G, and OSD_CP_B. In CLOR mode, the foreground color of each font is chosen from the color palette index 0 to 15 (FG Palette Color Index [3:0]); the background color from index 8 to 15 (BG Palette Color Index [2:0]). As in CCAP mode, the foreground color of each font is chosen from the color palette index 0 to 7 (FG Palette Color Index [2:0]); the background color of each font is chosen from the registers CCAP_BG0, CCAP_BG1, CCAP_BG2, and CCAP_BG3 with index (BG Color Index [1:0]). For CCAP_BG settings check Table 12.4.2.
Table 12.4.2 CCAP_BG Color Setting CCAP_BG Bits 0000 0001 0010 0011 0100 0101 0110 0111 Color Black Blue Green Aqua Red Fuchsia Yellow White CCAP_BG Bits 1000 1001 1010 1011 1100 1101 1110 1111 Color Transparent Royal Blue Medium Aquamarine Light Green Orange Hot Pink Silver Gray
The register, TRAN_INDEX, assigns the color palette index in which stands for transparent color.
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12.5 OSD MASKING AND ALPHA-BLENDING
The VX1138's OSD unit provides special masking function in the content displaying block. This is mainly for the scrolling function during closed caption displaying. The registers, OSDC_MASK_L, OSDC_MASK_R, OSDC_MASK_T, and OSDC_MASK_B define the boundary location for the four sides of the masking blocks.
The VX1138's OSD unit also support whole screen OSD alpha-blending with the source video. The blending factor, OSD_ALPHA, is programmable in registers and follows below equation.
OSD Displaying Color =
Video Color x OSD_ALPHA + OSD Color x ( 4 - OSD_ALPHA) 4
12.6 OSD MEMORY ACCESS
To configure the command memory and the user-programmable font memory, the VX1138 provides two methods by accessing registers. One method is through the direct memory accessing registers OSD_ADDR, OSD_DATA, and OSD_ATRI for command memory, and registers OSD_FONT_ADDR, OSD_FONT_DATA for user-programmable font memory. The other method is through the continuous writing mechanism with Continuous-Write Registers, CW_DEST, CW_INIT_ADDR, and CW_DATA.
12.6.1 DIRECT MEMORY ACCESS To directly change the content of the command memory, simply put the address in register OSD_ADDR and the data in registers OSD_DATA and OSD_ATRI. The OSD unit will send the data into the command memory right after the register writing operation of register OSD_DATA and OSD_ATRI. Similarily, to directly change the content of the user-programmable font memory, user simply puts the address in the register OSD_FONT_ADDR and the data in the register OSD_FONT_DATA from high byte to low byte. The OSD unit will send the data into the user-programmable font memory right after the writing operation of low byte of OSD_FONT_DATA.
12.6.2 CONTINUOUS WRITE MEMORY ACCESS For large amount of data writing operation such as font memory writing or full screen display change, the VX1138 provides continuous writing mechanism to save host access time and efforts. To use the Continuous-Write Registers, set the destination register, CW_DEST, and the initial address register,
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VX1138/VX1136
Product Specification High Quality Video Processor
CW_INIT_ADDR, consecutively, then write the data register, CW_DATA, repeatly. The continuous-writing mechanism will put data into the destination memory immediately after CW_DATA writing. For 16-bit data writing such as user-programmalbe font memory, the internal memory data writing will occur after every other CW_DATA writing (high byte prior to low byte). For example, to store a plus sign, "+", into the user-programmalbe font memory, the writing sequence are as Table 12.6.2.1. Table 12.6.2.1 Host Writing Sequence for Bitmap Host Command Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Address CW_DEST CW_INIT_ADDR CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA CW_DATA Data 010 00_0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0011_1111 1111_1100 0011_1111 1111_1100 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0001 1000_0000 0000_0000 0000_0000
Confidential
P38/P73
V1.22 090709
VX1138/VX1136
Product Specification
Host Command Write Write Address CW_DATA CW_DATA
High Quality Video Processor
Data 0000_0000 0000_0000
Confidential
P39/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
13 MEMORY INTERFACE
The external SDRAM interface of VX1138 provides the connection to standard Synchronous Dynamic Random-Access Memory (SDRAM) device. The interface supports 1M x 16 bit SDRAMs, supporting speed at least of -7 and CAS latency of 2. The memory-usage register, MEM_USAGE, configures SDRAM model being used, and partial functions may be inactivated between models (Table 13.1). See Figure 13.1 for SDRAM connection diagram.
VX1122 SDRAM _RAS SDRAM _CAS SDRAM _W E SDRAM _A[10:0] SDRAM _D[15:0] SDRAM _CLK SDRAM _BA
SDRAM 1M x 16 /RAS /CAS /W E A[10:0] D[15:0] CLK BA UDQM LDQM /CS CKE
GND
VDD
Figure 13.1 SDRAM Connection Diagram
Confidential
P40/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
14 TIMING CONTROLLER
The controlling signals applied to panel are generated by timing controller. STHR/L, POL, LD and VOCLK are controlling signals for source. Register LR (REG0xC0.1) set left-scan or right-scan by enable one of STHR/L. STVL/R, CKV and OEV are controlling signals for gate driver.
Confidential
P41/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
15 REGISTER DESCRIPTION
15.1 PROGRESSIVE VIDEO PROCESSOR REGISTER (CHIP ADDRESS = 0X32)
15.1.1 REGISTER MAP
Addr. (Hex) 01 03 04 05 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 20 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 Name RST1 RST3 GBL0 GBL1 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 INA INB INC IND INE DEI0 PADJ01 PADJ02 PADJ03 PADJ04 PADJ05 PADJ06 PADJ07 PADJ08 PADJ09 PADJ0A PADJ0B PADJ0C PADJ0D PADJ0E PADJ0F PADJ10 PADJ11 PADJ12 PADJ13 PADJ14 PADJ15 Def. (Hex) 00 F1 1C 01 20 00 00 03 5A 8A 00 00 28 00 00 00 00 00 00 00 80 80 80 A0 18 46 64 00 FF 00 80 80 80 80 80 80 60 5F 37 14 00 CMUX_INV R_LEVEL G_LEVEL B_LEVEL PADJ_PATT _EN CTIEXT BKXON CTI_Y BKXAUTO YDELAY [2:0] BKXLVL BKXMAX BKXTPIN BKXSLP BKXPCONT R_BRIGHTNESS G_BRIGHTNESS B_BRIGHTNESS R_CONTRAST G_CONTRAST B_CONTRAST SKIN_ADJ NO_VIDEO AUTO_BLUE INFC_PAT PG_IN
PASS_DEINT
Bit Map 7 DEI_ON TCON_EN NTSCPAL 6 RELX_ON DCLK_INV VOHS_SEL VICLKP INFMT
-
5 MCLK_ON
4 OSD_ON GPO1_SEL CLKDSRC SET_NP
3 D2OCLK
2 GPO1_EN
1 GPO0_EN GPO0_SEL GPO2_SEL
0 ACLK_ON
RESET / CLEAR
AUTO_NP
VICLKF
SQ_EN VIHSP
UVFMT -
INSYN VIHS_OFST[7:0]
VIVSP/ VIFDP
V4_UV_INV INFIELD_INV
-
MIL_EN MHIL [7:0] MHSL VIVS_OFST[7:0] VIVS_OFST[10:8]
MHIL [11:8]
VIHS_OFST[10:8] MVIL [10:8]
VSYNC_LEN MVIL [7:0] MVIAL [10:8] MHIAL [7:0] MVIAL [7:0] IN_PATT_E ICLK_DETECT N R_INV G_INV B_INV DEINT_MODE CONTRAST SATURATION HUE CTI_C BRIGHTNESS
MHIAL [10:8]
IN_PATT_MODE RGBIN_MUX -
VNR
UVINV
PADJ_PATT_MODE
Confidential
P42/P73
V1.22 090709
VX1138/VX1136
Product Specification
Addr. (Hex) 48 49 4A 4B 4C 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 75 76 77 78 79 7A 7B 7C Name PEAK01 PEAK02 PEAK03 PEAK04 PEAK06 OSD00 OSD01 OSD02 OSD03 OSD04 OSD05 OSD06 OSD07 OSD08 OSD09 OSD0A OSD0B OSD0C OSD0D OSD0E OSD0F OSD10 OSD11 OSD12 OSD13 OSD14 OSD15 OSD16 OSD17 OSD18 OSD19 OSD1A OSD1B OSD1C OSD1D OSD1E OSD1F OSD20 OSD21 OSD22 OSD23 OS00 OS01 OS02 OS03 OS04 OS05 OS06 OS07 Def. (Hex) 20 00 00 00 7F 20 20 00 04 00 A0 40 04 10 08 10 00 68 84 08 21 20 B0 33 01 FF 01 FF 89 AB 28 6E 6E 6E 00 00 00 00 00 00 00 FF FF FF FF FF FF FF FF OSD_FONT_ADDR [7:0] OSD_FONT_DATA [15:8] OSD_FONT_DATA [7:0] PWM0_H [15:8] PWM0_H [7:0] PWM1_H [15:8] PWM1_H [7:0] PWM0_L [15:8] PWM0_L [7:0] PWM1_L [15:8] PWM1_L [7:0] CCAP_BG0 CCAP_BG2 TRAN_INDEX OSD_CP_R OSD_CP_G OSD_CP_B OSD_ADDR OSD_DATA OSD_ATRI OSD_FONT_ADDR [10:8] OSDC_MASK_L [9:8] OSDB_POSX [9:8] OSDC_POSX [9:8] OSDC_POSX [7:0] OSDC_POSY [7:0] OSDB_MADR OSDB_SIZEX OSDB_POSY [9:8] OSDB_POSX [7:0] OSDB_POSY [7:0] OSDC_MASK_R [9:8] OSDC_MASK_T [9:8] OSDC_MASK_B [9:8] OSDC_MASK_L [7:0] OSDC_MASK_R [7:0] OSDC_MASK_T [7:0] OSDC_MASK_B [7:0] CCAP_BG1 CCAP_BG3 OSD_CP_INDEX OSDT_POSX [9:8] OSDT_POSX [7:0] OSDT_POSY [7:0] OSDC_MADR OSDC_SIZEX OSDC_SIZEY OSDC_POSY [9:8] OSD_BLINK POSD CCMODE OSD_X2 OSDT_MADR OSDT_SIZEX OSDT_POSY [9:8] Bit Map 7 PEAK_EN 6 5 4 3 PEAK_CLIP_MIN PEAK_ADJ1 PEAK_ADJ2 PEAK_ADJ3 PEAK_CLIP_MAX OSD_ALPHA OSDT_EN OSDC_EN OSDB_EN 2 1 0
High Quality Video Processor
Confidential
P43/P73
V1.22 090709
VX1138/VX1136
Product Specification
Addr. (Hex) 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 91 92 A0 A1 A2 A3 A4 A5 A6 A7 AA C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 Name OS08 OS09 OS0A OS0B OS0C OS0D OS0E OS0F OS10 OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 OS1A MC1 MC2 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SCA TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC0A TC0B TC0C TC0D TC0E TC0F TC10 Def. (Hex) F0 00 00 71 01 00 10 00 00 00 00 00 00 00 50 00 20 90 00 00 E8 18 70 1F 43 66 63 1E 02 80 00 00 FC 08 00 0A 10 00 11 50 00 10 30 1C 31 E8 2C OEV_START[11:8] OEV_START[7:0] OEV_END[7:0] STV_START[11:8] STV_START[7:0] STV_END[7:0] STV_ON OEV_END[11:8] CKV_START[11:8] CKV_START[7:0] CKV_END[7:0] STV_END[11:8] LD_START[11:8] LD_START[7:0] LD_END[7:0] CKV_END[11:8] UP_SCALE OEN_MODE STV_MODE STV_DEL POL_ALT[11:8] STH_START[7:0] POL_ALT[7:0] LD_END[11:8] H_TOTAL[11:8] HORIZONTAL_SF VERTICAL_SF[15:8] VERTICAL_SF[7:0] UD STH_START[11:8] LR SCLK_P SYNC_INV FSTOP MC_EN DI_EN SMODE H_ACT [7:0] H_TOTAL[7:0] H_ACT[11:8] HS_WIDTH[8] -
High Quality Video Processor
Bit Map 6 5 4 3 2 1 0
7
HBLANK_ OFST [4]
OCLKP OUV_INV
OS_PAT_VALUE OS_PAT_E ROUT_OFF GOUT_OFF BOUT_OFF N POUT_B_IN POUT_G_IN POUT_R_IN . POUT_RGB_MUX. V V V CBLANK_ HBLANK_OFST[3:0] EN DOUT_ VOCLKP HSYNCP HBLANKP VSYNCP VBLANKP VOVALIDP OFF OFMT CSYNC_EN CLAMP DITHER VS_WIDTH HSHIFT[7:0] VSHIFT[7:0] BOTTOM_MASK[7:0] TOP_MASK[7:0] LEFT_MASK[7:0] CLUT_ WIDTH HS_WIDTH[7:0] HSHIFT[10:8] VSHIFT[10:8] LEFT_MASK[9:8] RIGHT_MASK[9:8] BOTTOM_MASK[9:8] RIGHT_MASK[7:0] CLUT_ FRM_MODE MODE YSYNC_LVL -
P656_EN
-
OTRI
VOE_EN
TOP_MASK[9:8]
Confidential
P44/P73
V1.22 090709
VX1138/VX1136
Product Specification
Addr. (Hex) D1 D2 D3 D4 E0(R) E1(R) E2(R) E3(R) E4(R) Name TC11 TC12 SYC0 SYC1 CCD0 CCD1 CCD2 CCD3 CCD4 Def. (Hex) 00 00 AE 01 D4 00 B3 9F 00 32 5A D0 00 16 01 30 43 1F 1F 22 73 53 80 01 01 00 00 00 CW_DEST CW_DATA PT_INTLEN CW_INIT_ADDR [7:0] CW_INIT_ADDR[10:8] PT_VLEN[11:8] PT_VLEN[7:0] PT_VACT[7:0] PT_RGBVAL[7:0] PT_INCVAL PAT_EN GEN_SYNC PT_VPOL PT_HLEN[11:8] PT_HLEN[7:0] PT_HACT[7:0] PT_VACT[11:8] VSIN_LENGTH[10:8] HSIN_LENGTH[11:8] HSIN_LENGTH[7:0] HSIN_ACT[7:0] VSIN_ACT[7:0] PT_HPOL PAT_MODE PT_HACT[11:8] VSIN_ACT[10:8] VSIN_LENGTH[7:0]
VD_SYN_EN
High Quality Video Processor
Bit Map 6 OEV_P FIELD_INV HTOTAL[10:8] V_TOTAL[10:8] H_TOTAL[7:0] H_ACTIVE[7:0] V_TOTAL[7:0] HSIN_ACT[11:8] 5 CKV_P 4 STV_P H_ACTIVE[9:8] 3 2 POL_P 1 LD_P 0 POL_MODE STH_P
7 -
VSYNC_DEL[7:0] VSYNC_DEL[9:8]
E5(R) INFC11 E6(R) INFC12 E7(R) INFC13 E8(R) INFC14 E9(R) INFC15 EA(R) INFC16 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FD FE FF PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 CW1 CW2 CW3
Confidential
P45/P73
V1.22 090709
VX1138/VX1136
Product Specification
15.1.2.1 GLOBAL REGISTERS
Addr. (Hex) 01 02 03 Def. (Hex) 02 F1 Bit Map 4 3 RESET / CLEAR RELX_ON MCLK_ON OSD_ON D2OCLK
High Quality Video Processor
Name RST1 RST2 RST3
7 DEI_ON
6
5
2
1
0
OCLK_DIV GPO1_EN GPO0_EN
ACLK_ON
RESET CLEAR
Software reset all circuits by writing 5Ah Software reset all circuits other than registers by writing A5h
OCLK_DIV
Output clock = (PLL2 output clock) / (OCLK_DIV[3:0]+1)
DEI_ON
Deinterlace block enable
RELX_ON
Scaler block enable
MCLK_ON
Memory clock enable
OSD_ON
OSD block enable
D2OCLK
Set OCLK = DLCK
GPO1_EN
GPO1_enable
GPO0_EN
GPO0_enable
ACLK_ON
All PLL clocks enable
Def. Addr. Name (He (Hex) 7 6 x) 04 GBL0 1C DVLK_INV 05 GBL1 01 TCON_EN VOHS_SEL
Bit Map 5 4 GPO1_SEL 3 2 1 GPO0_SEL GPO2_SEL 0
DCLK_INV
Inverse dclk
GPO1_SEL, GPO2_SEL GPO0_SEL
General-purpose output pin function selection. For configuration details see Table 15.2.1.1.
Confidential
P46/P73
V1.22 090709
VX1138/VX1136
Product Specification
Table 15.2.1.1 GPO_SEL and GPO signal GPO2_SEL 0 1(df.) 2 3 4 5 6 7 GPO2 HBLANK GCSYNC VBLANK PWM0 PWM1 VOVALID 0 1 GPO1_SEL 0 1 2 3(df.) 4 5 6 7 GPO1 HBLANK GCSYNC VBLANK PWM0 PWM1 VOVALID 0 1 GPO0_SEL 0 (df.) 1 2 3 4(df.) 5 6 7 GPO0 HBLANK GCSYNC VBLANK PWM0 PWM1 VOVALID 0 1
High Quality Video Processor
TCON_EN
Enable the Timing Controller function, and I/O pins
VOHS_SEL
Select the output hsync type 0 : general horizontal sync 1 : Composite horizontal sync, depend on GPO2_SEL
15.1.2.2 INPUT FORMAT REGISTERS
Addr. (Hex) 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Def. (Hex) 20 00 00 03 5A 8A 00 00 28 00 00 00 00 00 00 PG_IN PASS_DEI NT V4_UV_IN INFIELD_I V NV Bit Map 4 3 SET_NP VICLKF INSYN VIHS_OFST [7:0] MIL_EN MHIL[7:0] MHSL VIVS_OFST [7:0] VIVS_OFST [10:8] VSYNC_LEN INFC_PAT MVIL[7:0] MVIAL[10:8] MHIAL[7:0] MVIAL[7:0] INFC_PATT ICLK_DETECT _EN R_INV G_INV B_INV VIHS_OFST [10:8] MVIL[10:8] MHIAL[10:8] MHIL[11:8]
Name IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 INA INB INC IND INE
7 NTCPAL
6 VICLKP INFMT
5 AUTO_NP
2 SQ_EN VIHSP
1 UVFMT -
0 VIVSP/ VIFDP
NO_VIDEO AUTO_BLUE -
INFC_PATT_MODE RGBIN_MUX
NTSCPAL
0 1
Input video is in NTSC format (read only) Input video is in PAL format (read only)
Confidential
P47/P73
V1.22 090709
VX1138/VX1136
Product Specification
VICLKP 0 1 Normal (df.) Inverse VICLK pin polarity
High Quality Video Processor
AUTO_NP
0 1
Manually setting input video standard from register SET_NP Auto-detecting input video standard (df.)
SET_NP
0 1
Manually setting input standard to NTSC (df.) Manually setting input standard to PAL
VICLKF
0 1
VICLK is 2x input data rate VICLK is 1x input data rate (df.)
SQ_EN
0 1
Non-square-pixel mode (df.) Square-pixel mode
UVFMT
0 1
Un-sign (df.) Sign
INFMT[2:0]
Video input format 0 1 2 3 6 7 8-bit ITU-R BT.656 8-bit YUV + VIHS/VIVS/VIFIELD : ITU-R BT.601 16-bit Y/UV + VIHS + VIVS 24-bit YUV progressive input CCD bayer format input 24-bit RGB progressive input
INSYN[1:0]
Video input synchronization format 0 1 2 3 Equaled VIVS (262.5 VIHSs per VIVS) (df.) Non-equaled VIVS (262/263 VIHSs per VIVS) Equaled VIFIELD (262.5 VIHSs per VIFIELD) Non-equaled VIFIELD (262/263 VIHSs per VIFIELD)
VIHSP
Pin VIHS polarity
VIVSP / VIFDP
Pin VIVS / VIFD polarity
Confidential
P48/P73
V1.22 090709
VX1138/VX1136
Product Specification
VIHS_OFST[10:0]
High Quality Video Processor
Offset for screening valid video input data in each line
VIVS_OFST[10:0]
Offset for screening valid video input lines in each field
V4_UV_INV
Inverse input video U/V data
INFIELD_INV
Inverse the input filed signal
MIL_EN
Manually setting length of input signal enable
MHIL[11:0]
Manually setting period of VIHS value
MHSL[7:0]
Manually setting sync-length of VIHS value (Interlace Only)
MHIAL[10:0]
Manually setting active-length of VIHS value (Progressive only)
MVIL[10:0]
Manually setting period of VIVS value
MVIAL[10:0]
Manually setting active-length of VIVS value
INFC_PAT[1:0]
input format color pattern select 0 1 2 3 Normal Y only C only Blue screen
NO_VIDEO
No Video signal input, when there exist VICLK, read only.
AUTO_BLUE
Auto set to blue screen, when NO_VIDEO detected.
ICLK_DETECT[1:0]
The auto_detect input clock result : 0 1 2 3 No input clock found VICLK detected RGBINCLK detected XTALIN detected
Confidential
P49/P73
V1.22 090709
VX1138/VX1136
Product Specification
PG_IN
High Quality Video Processor
Input signal is progressive not interlace
PASS_DEINT
Pass the deinterlace block, used for progressive input
INFC_PATT_EN
Enable the input pattern generation
INFC_PATT_MODE[3:0]
Select the input pattern generation type 0 1 2 3 4 5 gray frame increase 1 each 1 clock vertical bar increase 1 every 2 clock vertial bar increase 1 every 4 clock vertial bar increase 1 every 8 clockl vertial bar color bar
R_INV
Invert the RIN[7:0] input pin order to [0:7]
G_INV
Invert the GIN[7:0] input pin order to [0:7]
B_INV
Invert the BIN[7:0] input pin order to [0:7]
RGBIN_MUX[2:0]
Swap the RIN,GIN,BIN input data bus.
RGBIN_MUX 0 1 2 3 4 5 6 7
R R R G G B B R G
G G B R B R G R G
B B G B R G R R G
Confidential
P50/P73
V1.22 090709
VX1138/VX1136
Product Specification
15.1.2.3 DEINTERLACE REGISTERS
Addr. (Hex) 20 Def. (Hex) 00 Bit Map 7 6 5 4 DEINT_MODE 3 2 1 0 -
High Quality Video Processor
Name DEI0
DEINT_MODE
Deinterlace operating mode 0 1 2 3 Motion-adaptive 3D deinterlace mode Inter-field interpolation mode Intra Edge-preserving pixel interpolation mode Reserved
15.1.2.4 PICTURE ADJUSTMENT REGISTERS
Addr. (Hex) 31 32 33 34 35 Def. (Hex) 80 80 80 A0 18 Bit Map 4 3 BRIGHTNESS CONTRAST SATURATION HUE YDELAY [2:0] CTI_C VNR UVINV
Name PADJ01 PADJ02 PADJ03 PADJ04 PADJ05
7
6
5
2
1
0
CTIEXT BKXON
CTI_Y BKXAUTO
BRIGHTNESS
Brightness adjustment
CONTRAST
Contrast adjustment
SATURATION
Saturation adjustment
HUE
Hue adjustment
YDELAY[2:0]
Offset between Y and C, for engineering usage
CTIEXT
CTI mode select
CTI_Y
Color transient improvement (CTI) enable for Y
CTI_C
Color transient improvement (CTI) enable for C
VNR
Video noise reduction (VNR) enable
Confidential
P51/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
UVINV
UV inversion
Addr. (Hex) 35 36 37 38 39 3A (R)
Name PADJ05 PADJ06 PADJ07 PADJ08 PADJ09 PADJ0A
Def. (Hex) 18 46 64 00 FF 00
7 BKXON
6 BKXAUTO
5
Bit Map 4 3 YDELAY [2:0] BKXLVL BKXMAX BKXTPIN BKXSLP BKXPCONT
2 CEN
1 VNR
0 UVINV
BKXON
Black-level extension (BLE) enable
BKXAUTO
0 1
Manually setting black-level extension Automatically setting black-level extension
BKXLVL
Black-level threshold. Luminance below the value is considered as black.
BKXMAX
The maximum location of adaptive turnaround point
BKXTPIN
Parameter for manually setting black-level extension
BKXSLP
The slope of the transform function in BLE section
BKXPCONT
Readout parameter for manually setting black-level extension
Addr. (Hex) 3B 3C 3D 3E 3F 40
Name PADJ0B PADJ0C PADJ0D PADJ0E PADJ0F PADJ10
Def. (Hex) 80 80 80 80 80 80
7
6
5
Bit Map 4 3 R_BRIGHTNESS G_BRIGHTNESS B_BRIGHTNESS R_CONTRAST G_CONTRAST B_CONTRAST
2
1
0
R_BRIGHTNESS
R channel output brightness adjustment
Confidential
P52/P73
V1.22 090709
VX1138/VX1136
Product Specification
G_BRIGHTNESS
High Quality Video Processor
G channel output brightness adjustment
B_BRIGHTNESS
B channel output brightness adjustment
R_CONTRAST
R channel output contrast adjustment
G_CONTRAST
G channel output contrast adjustment
B_CONTRAST
B channel output contrast adjustment
Addr. (Hex) 41 42 43 44 45
Name PADJ11 PADJ12 PADJ13 PADJ14 PADJ15
Def. (Hex) 60 5F 37 14 00
Bit Map 7 6 CMUX_INV 5 4 3 2 SKIN_ADJ 1 0
-
R_LEVEL G_LEVEL B_LEVEL PADJ_PAT T_EN
PADJ_PATT_MODE
CMUX_INV
Skin tone Cb/Cr change
SKIN_ADJ
Skin tone region enhancement level
R_LEVEL
Red threshold for skin tone adjustment
G_LEVEL
Green threshold for skin tone adjustment
B_LEVEL
Blue threshold for skin tone adjustment
PADJ_PATT_EN
Enable PADJ patten generation output
PADJ_PATT_MODE
Select the PADJ pattern generation type 0 1 2 3 4 5 gray frame increase 1 each 1 clock vertical bar increase 1 every 2 clock vertial bar increase 1 every 4 clock vertial bar increase 1 every 8 clockl vertial bar color bar
Confidential
P53/P73
V1.22 090709
VX1138/VX1136
Product Specification
15.1.2.5 PICTURE ADJUSTMENT REGISTERS
Addr. (Hex) 48 49 4A 4B 4C Def. (Hex) 7 20 PEAK_EN 00 00 00 7F Bit Map 6 5 4 3 2 PEAK_CLIP_MIN PEAK_ADJ1 PEAK_ADJ2 PEAK_ADJ3 PEAK_CLIP_MAX 1 0
High Quality Video Processor
Name PEAK01 PEAK02 PEAK03 PEAK04 PEAK06
PEAK_EN
Horizontal sharpening enable
PEAK_CLIP_MIN
Clipping filter parameter
PEAK_ADJ1
Weighting of horizontal video sharpening in high-frequency
PEAK_ADJ2
Weighting of horizontal video sharpening in mid-frequency
PEAK_ADJ3
Weighting of horizontal video sharpening in low-frequency
PEAK_CLIP_MAX
Clipping filter parameter
15.1.2.6 OSD REGISTERS
Addr. (Hex) 50 51 Def. (Hex) 20 20 Bit Map 7 6 5 OSD_BLINK POSD 4 CCMODE 3 OSD_X2 2 1 0 OSD_ALPHA OSDT_EN OSDC_EN OSDB_EN
Name OSD00 OSD01
OSD_BLINK
OSD blinking rate
OSD Blinking Rate =
30 Hz OSD_BLINK x 4
OSD_ALPHA
OSD alpha-blending. See following equation. OSD_ALPHA [3:2] for foreground; OSD_ALPHA [1:0] for background.
Confidential
P54/P73
V1.22 090709
VX1138/VX1136
Product Specification
OSD Displaying Color =
High Quality Video Processor
Video Color x OSD_ALPHA + OSD Color x ( 4 - OSD_ALPHA) 4
POSD
0 1
Interlaced OSD Progressive OSD
CCMODE
Command memory configuration 0 1 COLR Mode CCAP Mode
OSD_X2
OSD font-size selection 0 1 Small font (16 pixel x 20 pixel) Large font (32 pixel x 40 pixel)
OSDT_EN
OSD title block display enable
OSDC_EN
OSD content block display enable
OSDB_EN
OSD bar block display enable
Addr. (Hex) 52 53 54 55 56
Name OSD02 OSD03 OSD04 OSD05 OSD06
Def. (Hex) 00 04 00 A0 40
7 -
6 -
Bit Map 4 3 2 OSDT_MADR OSDT_SIZEX OSDT_POSX [9:8] OSDT_POSX [7:0] OSDT_POSY [7:0] 5
1
0
OSDT_POSY [9:8]
OSDT_MADR
OSD title block initial address in OSD command memory
OSDT_SIZEX
OSD title block horizontal length in character. Valid settings are 01h - 26h for small fonts; 01h - 13h for large fonts.
OSDT_POSX
OSD title block horizontal initial position. Incrementing by 1 reflects 1 pixels shifting rightwards. Minimum value is 03h.
OSDT_POSY
OSD title block vertical initial position. Incrementing by 1 reflects 1
Confidential
P55/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
lines shifting downwards. Minimum value is 01h.
Addr. (Hex) 57 58 59 5A 5B 5C Def. (Hex) 04 10 08 10 00 68 Bit Map 4 3 2 OSDC_MADR OSDC_SIZEX OSDC_SIZEY OSDC_POSX [9:8] OSDC_POSX [7:0] OSDC_POSY [7:0] 5
Name OSD07 OSD08 OSD09 OSD10 OSD11 OSD12
7 -
6 -
1
0
OSDC_POSY [9:8]
OSDC_SIZEX
OSD content block horizontal length in character
OSDC_SIZEY
OSD content block vertical length in character. Valid settings are 01h - 15h for small fonts; 01h - 0Ah for large fonts.
OSDC_MADR
OSD content block initial address in OSD command memory
OSDC_POSX
OSD content block horizontal initial position. Incrementing by 1 reflects 1 pixels shifting rightwards. Minimum value is 03h.
OSDC_POSY
OSD content block vertical initial position. Incrementing by 1 reflects 1 lines shifting downwards. Minimum value is 01h.
Addr. (Hex) 5D 5E 5F 60 61
Name OSD13 OSD14 OSD15 OSD16 OSD17
Def. (Hex) 84 08 21 20 B0
7 -
6 -
Bit Map 4 3 2 OSDB_MADR OSDB_SIZEX OSDB_POSX [9:8] OSDB_POSX [7:0] OSDB_POSY [7:0] 5
1
0
OSDB_POSY [9:8]
OSDB_SIZEX
OSD bar block horizontal length in character
OSDB_MADR
OSD bar block initial address in OSD command memory
OSDB_POSX
OSD bar block horizontal initial position. Incrementing by 1 reflects 1 pixels shifting rightwards. Minimum value is 03h.
OSDB_POSY
OSD bar block vertical initial position. Incrementing by 1 reflects 1 lines shifting downwards. Minimum value is 01h.
Confidential
P56/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
Addr. (Hex) 62 63 64 65 66
Name OSD18 OSD19 OSD20 OSD21 OSD22
Def. (Hex) 33 01 FF 01 FF
7 6 OSDC_MASK_L [9:8]
Bit Map 5 4 3 2 OSDC_MASK_R [9:8] OSDC_MASK_T [9:8] OSDC_MASK_L [7:0] OSDC_MASK_R [7:0] OSDC_MASK_T [7:0] OSDC_MASK_B [7:0]
1 0 OSDC_MASK_B [9:8]
OSDC_MASK_L
OSD content block masking boundary location for left-hand-side
OSDC_MASK_R
OSD content block masking boundary location for right-hand-side
OSDC_MASK_T
OSD content block masking boundary location for top side
OSDC_MASK_B
Addr. (Hex) 67 68 Def. (Hex) 89 AB
OSD content block masking boundary location for bottom side
Bit Map 7 6 5 CCAP_BG0 CCAP_BG2 4 3 2 1 CCAP_BG1 CCAP_BG3 0
Name OSD23 OSD24
CCAP_BG0
OSD background color 0 in CCAP mode
CCAP_BG1
OSD background color 1 in CCAP mode
CCAP_BG2
OSD background color 2 in CCAP mode
CCAP_BG3
Addr. (Hex) 69 6A 6B 6C Def. (Hex) 28 6E 6E 6E
OSD background color 3 in CCAP mode
Bit Map 7 6 5 TRAN_INDEX 4 3 2 1 OSD_CP_INDEX 0
Name OSD25 OSD26 OSD27 OSD28
OSD_CP_R OSD_CP_G OSD_CP_B
TRAN_INDEX
Define color palette index in which stands for transparent color
OSD_CP_INDEX
Specify color index in color palette
OSD_CP_R
Setting color R to which index specified in OSD_CP_INDEX
Confidential
P57/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
OSD_CP_G
Setting color G to which index specified in OSD_CP_INDEX
OSD_CP_B
Setting color B to which index specified in OSD_CP_INDEX
Addr. (Hex) 6D 6E 6F 70 71 72 73
Name OSD29 OSD30 OSD31 OSD32 OSD33 OSD34 OSD35
Def. (Hex) 00 00 00 00 00 00 00
7
6
5
-
-
-
Bit Map 4 3 OSD_ADDR OSD_DATA OSD_ATRI OSD_FONT_ADDR [7:0] OSD_FONT_DATA [15:8] OSD_FONT_DATA [7:0]
2
1
0
OSD_FONT_ADDR [10:8]
OSD_ADDR
OSD command memory address
OSD_DATA
OSD command memory data
OSD_ATRI
OSD command memory attribute
OSD_FONT_ADDR
OSD font memory address
OSD_FONT_DATA
OSD font memory data
15.1.2.7 OUTPUT FORMAT REGISTERS
Addr. (Hex) 75 76 77 78 79 7A 7B 7C Def. (Hex) FF FF FF FF FF FF FF FF Bit Map 4 3 PWM0_H [15:8] PWM0_H [7:0] PWM1_H [15:8] PWM1_H [7:0] PWM0_L [15:8] PWM0_L [7:0] PWM1_L [15:8] PWM1_L [7:0]
Name OS00 OS01 OS02 OS03 OS04 OS05 OS06 OS07
7
6
5
2
1
0
PWM0_H
Number of clocks in logic-1 for PWM0 signal
Confidential
P58/P73
V1.22 090709
VX1138/VX1136
Product Specification
PWM0_L
High Quality Video Processor
Number of clocks in logic-0 for PWM0 signal
PWM1_H
Number of clocks in logic-1 for PWM1 signal
PWM1_L
Number of clocks in logic-0 for PWM1 signal PWM0 and PWM1 are available at GPO pins. See register description for GPO1_SEL, and GPO2_SEL for GPO settings.
Addr. (Hex) 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
Name OS08 OS09 OS0A OS0B OS0C OS0D OS0E OS0F OS10 OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 OS1A
Def. (Hex) F0 00 00 71 01 00 10 00 00 00 00 00 00 00 50 00 20 90 00
7
HBLANK_ OFST [4]
OCLKP OUV_INV
Bit Map 4 3 2 1 0 OUT_PAT_VAL OS_PAT_E ROUT_OF GOUT_OF BOUT_OFF N F F OUT_B_IN OUT_G_IN OUT_R_IN OUT_RGB_MUX V V V CBLANK_ LCDPWR_ HBLANK_OFST[3:0] LCDPWR_DLY EN EN DOUT_ HSYNCP HBLANKP VSYNCP VBLANKP VOVALIDP OFF CSYNC_E OFMT CLAMP DITHER N VS_WIDTH 6 5 HSHIFT[7:0] VSHIFT[7:0] BOTTOM_MASK[7:0] TOP_MASK[7:0] LEFT_MASK[7:0] CLUT_ WIDTH HS_WIDTH[7:0] HSHIFT[10:8] VSHIFT[10:8] LEFT_MASK[9:8] RIGHT_MASK[9:8] BOTTON_MASK[9:8] RIGHT_MASK[7:0] CLUT_ FRM_MODE MODE YSYNC_LVL -
P656_EN HS_WIDTH [8]
-
OTRI
VOE_EN
TOP_MASK[9:8]
OUT_PAT_VAL
Output pattern value : P
OUT_PAT_EN
Enable output internal building RGB pattern
OUT_PAT_MODE
RGB building pattern mode select
OUT_PAT_MODE 0
R 0
G 0
B 0
Confidential
P59/P73
V1.22 090709
VX1138/VX1136
Product Specification
1 2 3 4 5 6 7 0 0 0 P P P P
High Quality Video Processor
0 P P 0 0 P P P 0 P 0 P 0 P
OUT_RGB_MUX
RGB output pin mux select
OUT_RGB_MUX 0 1 2 3 4 5 6 7
R R B G B G R G R
G G G R R B B G R
B B R B G R G G R
ROUT_OFF
Set the ROUT value to 0
GOUT_OFF
Set the GOUT value to 0
BOUT_OFF
Set the BOUT value to 0
OUT_R_INV
Inverse the DR[7:0] output pin 7~0 to 0~7
OUT_G_INV
Inverse the DG[7:0] output pin 7~0 to 0~7
OUT_B_INV
Inverse the DB[7:0] output pin 7~0 to 0~7
CBLANK_EN
CBLANK on pin HBLANK enable
HBLANK_OFST[4:0]
HBLANK offset value, df=7
Confidential
P60/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
LCDPWR_EN
LCD power-on delay enable
LCDPWR_DLY
LCD power-on delay adjustment 0 1 2 3 32 horizontal lines (0.5 ~ 1 ms) 65 horizontal lines (1 ~ 2 ms) 130 horizontal lines (2 ~ 4 ms) 260 horizontal lines (4 ~ 8 ms)
OCLKP
Internal Output clock polarity
DOUT_OFF
Digital video output disable
HSYNCP
Pin HSYNC polarity
HBLANKP
HBLANK (on GPO pin) polarity
VSYNCP
Pin VSYNC polarity
VBLANKP
VBLANK (on GPO pin) polarity
VOVALIDP
VOVALID (on GPO pin) polarity
OUV_INV
Inverse the Cb/Cr value
OFMT
Progressive video output format; see Table 15.2.5.1. Table 15.2.5.1 Output Format 3-Channel RGB 3-Channel 4:4:4 YPbPr (with embedded horizontal and vertical synchronization on Y 2-Channel 4:2:2 YUV (with additional HSYNC and VSYNC pins) 3-Channel 4:4:4 YUV (with additional HSYNC and VSYNC pins)
OFMT 0 1 Digital Port 2 3
CSYNC_EN
Enable the composite sync on hsync
CLAMP
Video output data clamping control
Confidential
P61/P73
V1.22 090709
VX1138/VX1136
Product Specification
0 1 2 3
High Quality Video Processor
Disable. Video output is in the range of 0 - 255. Video output is in the range of 16 - 235 (Y), 16 - 240 (UV) Video output is in the range of 1 - 254. Reserved
DITHER
Video output data dithering control; see Table 17.2.5.2.
Table 17.2.5.2 DITHER Dithering Option (G/Y:B/Pb/U:R/Pr/V) DITHER Dithering Option (G/Y:B/Pb/U:R/Pr/V) Disable Dithering to 24-bits (8-bits : 8-bits : 8-bits) 0 2 Dithering to 18-bits (6-bits : 6-bits : 6-bits) Dithering to 16-bits (6-bits : 5-bits : 5-bits) 1 3
HS_WIDTH[8:0]
Width of video output horizontal synchronization Actual synchronization-width = 13 + (HS_WIDTH x 4) in pixels
VS_WIDTH[7:0]
Width of video output vertical synchronization Actual synchronization-width = 1 + VS_WIDTH in lines
HSHIFT[10:0]
Video output horizontal shifting
VSHIFT[10:0]
Video output vertical shifting
BOTTOM_MASK[9:0]
Number of lines masked from the bottom of a frame
TOP_MASK[9:0]
Number of lines masked from the top of a frame
LEFT_MASK[9:0]
Number of pixels masked from the left-hand-side of a frame
RIGHT_MASK[9:0]
Number of pixels masked from the right-hand-side of a frame
CLUT_WIDTH
Color Look-Up Table (CLUT) data-width selection 0 1 8-bit 10-bit
CLUT_MODE
0 1
No CLUT Using 3-channel RAM as CLUT
P656_EN
Enable progressive 656 output
Confidential
P62/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
FRM_MODE
Output frame frequency mode 00 frame_rate 01 frame_rate/2 02 frame_rate/4
OTRI
Video outputs high impedance enable When OTRI is on, the digital video outputs, DR_V, DG_Y, DB_U, EXV, HSYNC, VSYNC, HBLANK, VBLANK, VOVALID, GPO0, GPO1, GPO2, and VOCLK, are forced high impedence.
YSYNC_LVL
The depth of Y synchronization in YPbPr output mode
VAL_STEP
The step size of pattern value
15.1.2.8 SDRAM INTERFACE REGISTERS
Addr. (Hex) 91 92 Def. (Hex) 00 E8 Bit Map 7 FSTOP MC_EN 6 DI_EN 5 4 3 2 1 0 -
Name MC1 MC2
FSTOP
Stop updating frame memory
MC_EN
Memory interface enable
DI_EN
Memory interface 3D deinterlace port enable
15.1.2.9 RELACS REGISTERS
Confidential
P63/P73
V1.22 090709
VX1138/VX1136
Product Specification
Addr. (Hex) A0 A1 A2 A3 A4 A5 A6 A7 AA Name SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SCA Def. (Hex) 7 18 70 1F 43 66 63 1E 02 80 UP_SCALE Bit Map 6 5 SMODE 4 3 2 1 0
High Quality Video Processor
H_ACT [7:0] H_TOTAL[7:0] H_TOTAL[11:8] HORIZONTAL_SF VERTICAL_SF[15:8] VERTICAL_SF[7:0] SCLK_P SYNC_INV H_ACT[11:8]
SMODE
Scaling mode selection 0 1 2 3 4 5 6 7 8 9 1x Scaling Down-scaling to 60Hz VGA (640 x 480) Up-Scaling to SVGA (800 x 600) Up-Scaling to XGA (1024 x 768) Up-Scaling to SXGA (1280 x 1024) Up-Scaling to 720P (1280 x 720) Up-Scaling to WSVGA (1366 x 768 ) Up-Scaling to WVGA (1600x1200) Up-Scaling to 1080P (1920x1080) Up-Scaling to WVGA (800 x 480)
10 - 15 Manual setting
H_ACT[11:0]
Manual setting horizontal active length
H_TOTAL[11:0]
Manual setting horizontal total length
UP_SCALE
horizontal and vertical up-scaling function enable
H_SF[7:0]
horizontal scaling factor 1
V_SF[15:0]
vertical scaling factor 1
SCLK_P
SCLK polarity
SYNC_INV
For scaler adjustment
15.1.2.10 TCON REGISTERS
Confidential
P64/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
Addr. (Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2
Name TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TC17 TC18
Def. (Hex) 00 00 FC 08 00 0A 10 00 11 50 00 10 30 1C 31 E8 2C 00 00
Bit Map 7 6 5 4 3 STV_DEL 2 1 UD 0 LR OEV_MODE STV_MODE
POL_ALT[11:8] STH_START[7:0] POL_ALT[7:0] LD_START[11:8] LD_START[7:0] LD_END[7:0] CKV_START[11:8] CKV_START[7:0] CKV_END[7:0] STV_START[11:8] STV_START[7:0] STV_END[7:0] STV_ON OEV_START[11:8] OEV_START[7:0] OEV_END[7:0] OEV_P CKV_P STV_P -
STH_START[11:8]
LD_END[11:8]
CKV_END[11:8]
STV_END[11:8]
OEV_END[11:8]
POL_P
LD_P
POL_MOD E STH_P
OEV_MODE
Select OEV signal type (df. = 00)
STV_MODE
Select STV pulse type (df. = 00)
STV_DLY
Set delay of STV pulse in unit of a scan line (df. =
0)
UD
Up/Down scan control
LR
Left/Right scan control
POL_ALT
POL alternates time
STH_START
STHR/STHL pulse starts time
LD_START
LD pulse starts time
LD_END
LD pulse ends time
CKV_START
CKV rising time
Confidential
P65/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
CKV_END
CKV falling time
STV_START
STVL/STVR pulse starts time (df. = 0)
STV_END
STVL/STVR pulse ends time (df. = 0)
STV_ON
Set the scan line on which STV pulse exist (df. = 0)
OEV_START
OEV pulse starts point
OEV_END
OEV pulse ends point
POL_MODE
0: POL alternates per 1-H trigger (df.) 1: POL alternates per 2-H trigger
OEV_P
To invert OEV pulse
CKV_P
To invert CKV pulse
STV_P
To invert STVL/STVR pulse
POL_P
To invert POL signal
LD_P
To invert LD signal
STH_P
To invert STHL/STHR pulse
15.1.2.11 SDRAM BYPASS REGISTERS
Addr. Name Def. Bit Map
Confidential
P66/P73
V1.22 090709
VX1138/VX1136
Product Specification
(Hex) D3 D4 SY0 SY1 (Hex) AE 01 7 6 5
High Quality Video Processor
4 3 VSYNC_DEL[7:0] 2 1 0
VD_SYN_E VFIELD_IN N V
VSYNC_DEL[9:8]
VSYNC_DEL[9:0]
Delay of input VSYNC
VD_SYN_EN
Enable bypass sdram mode
VFIELD_INV
Inverse input video field signal
15.1.2.12 CCD IN READ REGISTER
Addr. (Hex) E0 E1 E2 E3 E4 Def. (Hex) D4 00 B3 9F 00 Bit Map 7 6 H_TOTAL[10:8] V_TOTAL[10:8] 5 4 3 H_ACTIVE[10:8] 2 H_TOTAL[7:0] H_ACTIVE[7:0] V_TOTAL[7:0] 1 0
Name CCD0 CCD1 CCD2 CCD3 CCD4
H_TOTAL[10:0]
total pixel of CCD input horizontal line
H_ACTIVE[10:0]
active pixel of CCD horizontal line
V_TOTAL[10:0]
total line of CCD vertical
15.1.2.13 INPUT SIGNAL SIZE REGISTER (READ)
Addr. (Hex) E5(R) E6(R) E7(R) E8(R) E9(R) EA(R) Def. (Hex) 32 5A D0 00 16 01 Bit Map 7 6 5 HSIN_LENGTH[11:8] 4 3 2 1 HSIN_ACT[11:8] 0
Name INFC11 INFC12 INFC13 INFC14 INFC15 INFC16
-
HSIN_LENGTH[7:0] HSIN_ACT[7:0] VSIN_LENGTH[10:8] VSIN_LENGTH[7:0] VSIN_ACT[7:0]
VSIN_ACT[10:8]
HSIN_LENGTH[11:0]
Input Horizontal line total length
HSIN_ACT[11:0]
Input Horizontal line active length
Confidential
P67/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
VSIN_LENGTH[10:0]
Input vertical total line count
VSIN_ACT[10:0]
Input vertical active line count
15.1.2.14 MEDIAN FILTER CONTROL REGISTER
Addr. (Hex) EB EC Def. (Hex) 00 80 Bit Map 7 MED_EN 6
MED_MODE
Name MED0 MED1
5
4 MED_TH
3
2
1
0
MED_EN
Enable median filter
MED_MODE
Median filter mode select
MED_TH
Threshold for median filter use
15.1.2.15 OUTPUT PATTERN GENERATION CONTROL REGISTER
Addr. (Hex) F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 Def. (Hex) 30 43 1F 1F 22 73 53 80 01 01 PT_VLEN[11:8] PT_VLEN[7:0] PT_VACT[7:0] PT_RGBVAL[7:0] PT_INCVAL PT_INTLEN Bit Map 7 6 5 PT_VPOL 4 PT_HPOL PT_HLEN[7:0] PT_HACT[7:0] PT_VACT[11:8] 3 2 1 0 PAT_EN GEN_SYNC PAT_MODE PT_HACT[11:8]
Name PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9
PT_HLEN[11:8]
PAT_EN
Enable Internal pattern generation
GEN_SYNC
0 1
use original setting for sync length Use user setting register(F1~F7) value to generate
Confidential
P68/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
horizontal/vertical total length and sync length
PT_VPOL
output vsync polarity
PT_HPOL
output hsync polarity
PAT_MODE
Setting the pattern mode 0 1 2 3 4 5 6 Pure color Horizontal increment value line Vertical increment value line Boundary and center line Grid line Color bar of horizontal direction Color bar of vertical direction
PT_HLEN[11:0]
output horizontal total length
PT_HACT[11:0]
output horizontal active length
PT_VLEN[11:0]
output vertical total length
PT_VACT[11:0]
output vertical active length
PT_RGBVAL[7:0]
output pattern value
PT_INCVAL
The incremental value of pattern generation
PT_INTLEN
The interval length of pattern increase
15.1.2.16 CONTINUOUS WRITE REGISTERS
Addr. Name Def. Bit Map
Confidential
P69/P73
V1.22 090709
VX1138/VX1136
Product Specification
(Hex) FD FE FF CW1 CW2 CW3 (Hex) 00 00 00 7 6 5 CW_DEST 4
High Quality Video Processor
3 CW_INIT_ADDR [7:0] CW_DATA 2 1 0 CW_INIT_ADDR [10:8]
CW_DEST
Continuous write destination selection 0 1 2 3 4 5 6 7 None OSD command memory index OSD font memory CLUT R / Pr CLUT G / Y CLUT B / Pb CLUT all OSD command memory attribute
CW_INIT_ADDR
Continuous write initial address
CW_DATA
Continuous write data
Confidential
P70/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
16 ELECTRICAL CHARACTERISTICS
16.1 ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage For Digital Core (1.8V Nominal) Supply Voltage For Digital I/O (3.3V Nominal) Supply Voltage For Analog Core (3.3V Nominal) Input Voltage For Digital I/O (5V Tolerant) Input Voltage For Analog Core Junction Temperature Storage Temperature Lead Temperature (Vapor Phase Soldering, 40 Seconds) Electronic Discharge
Symbol VCCC VDDD VDDA VID VIA TJ TSTG TL TESD
Min -0.5 -0.5 -0.5 -0.5 -0.5 -40 -55 -2000
Max 2.3 4.0 4.0 VDDD + 0.5 VDDA + 0.5 125 125 215 2000
Unit V V V V V C C C V
16.2 RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage For Digital Core (1.8V Nominal) Supply Voltage For Digital I/O (3.3V Nominal) Supply Voltage For Analog Core (3.3V Nominal) Ambient Operation Temperature Package Case Temperature Total Power Dissipation
Symbol VCCC VDDD VDDA TA TA PTOT
Min 1.5 3.0 3.1 0 -
Typ 1.8 3.3 3.3 TBA
Max 2.1 3.6 3.5 70 115 -
Unit V V V C C W
Confidential
P71/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
16.3 DC CHARACTERISTICS
Parameter Input (I, IS, IPU, IPD) High Level Input Voltage Low Level Input Voltage Leakage Current1 Output (O1, OTS1) High Level Output Voltage Low Level Output Voltage Tri-State Output Leakage Current Input/TTL Output (I/O1, I/O2) High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Pull-Up/Down Resistor Pull-Up Resistor Pull-Down Resistor
1
Symbol
Min
Typ
Max
Unit
VIH VIL IL
0.65 VDDD 0
-
0.35VDDD 500
V V A
VOH VOL IL
2.4 -25
-
0.4 25
V V A
VIH VIL VOH VOL
0.65 VDDD 2.4 -
-
0.35VDDD 0.4
V V V V
RPU RPD
59 63
74 77
94 97
k k
No leakage current flown when input voltage is VDDD or 0. The maximum occurs at transitions.
Confidential
P72/P73
V1.22 090709
VX1138/VX1136
Product Specification High Quality Video Processor
17 PACKAGE
Confidential
P73/P73
V1.22 090709

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